Keyword : multiple-valued reconfigurable VLSI

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2278-2285
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
multiple-valued reconfigurable VLSIfine-grain reconfigurable VLSIglobal tree local X-net networklogic-in-memory architecture
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