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IEICE Trans

Vikram IYENGAR

Hierarchical Intellectual Property Protection Using Partially-Mergeable Cores
Vikram IYENGAR Hiroshi DATE Makoto SUGIHARA Krishnendu CHAKRABARTY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2632-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Protection
Keyword: 
core partitioning, embedded core testing, intellectual property, partially-mergeable cores, test access mechanism (TAM), 
 Summary | Full Text:PDF