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IEICE Trans

Masaki HASHIZUME

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
Fara ASHIKIN Masaki HASHIZUME Hiroyuki YOTSUYANAGI Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/08/01
Vol. E101-D  No. 8  pp. 2053-2063
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
3D stacked IC, open defects, design-for-testability, through-silicon via, electrical interconnect test, 
 Summary | Full Text:PDF
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines
Hiroyuki YOTSUYANAGI Kotaro ISE Masaki HASHIZUME Yoshinobu HIGAMI Hiroshi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2842-2850
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
resistive open, small delay fault, adjacent line, delay variation, anomaly detection, 
 Summary | Full Text:PDF
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical test, built-in test circuit, open defect, interconnect test, design for testability, 
 Summary | Full Text:PDF
SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faults, adjacent lines, test pattern generation, coupling capacitance, SAT-based ATPG, 
 Summary | Full Text:PDF
An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs
Tsu-Lin LI Masaki HASHIZUME Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 2026-2030
Type of Manuscript:  Special Section LETTER (Special Section on Dependable Computing)
Category: 
Keyword: 
NROM, data inversion, fault masking, yield, 
 Summary | Full Text:PDF
On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Hiroyuki YOTSUYANAGI Hiroyuki MAKIMOTO Takanobu NIMIYA Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
delay testing, time-to-digital converter, boundary scan, design for testability, 
 Summary | Full Text:PDF
Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
Hiroyuki YOTSUYANAGI Masayuki YAMAMOTO Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 10-16
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
BIST-aided scan test, scan chain ordering, test data reduction, compatible flip-flops, test pattern generation, 
 Summary | Full Text:PDF
Genetic State Reduction Method of Incompletely Specified Machines
Masaki HASHIZUME Teruyoshi MATSUSHIMA Takashi SHIMAMOTO Hiroyuki YOTSUYANAGI Takeomi TAMESADA Akio SAKAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6  pp. 1555-1563
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
incompletely specified machine, maximal compatible set, state reduction, 
 Summary | Full Text:PDF
Lead Open Detection Based on Supply Current of CMOS LSIs
Masao TAKAGI Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6  pp. 1330-1337
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
lead open, CMOS LSI, supply current test, electric field, 
 Summary | Full Text:PDF
Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits
Masaki HASHIZUME Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 571-579
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword: 
feedback bridging fault, combinational circuit, logical oscillation, 
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Test Sequence Generation for Test Time Reduction of IDDQ Testing
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 537-543
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
IDDQ testing, bridging faults, switching current, supply current test, CMOS circuits, 
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Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field
Hiroyuki YOTSUYANAGI Taisuke IWAKIRI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2666-2673
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
open defects, supply current test, CMOS circuits, electric field, 
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CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply
Masaki HASHIZUME Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1542-1550
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
open defect, CMOS, supply current test, electric field, 
 Summary | Full Text:PDF
IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
Masaki HASHIZUME Teppei TAKEDA Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Yukiya MIURA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1534-1541
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Current Test
Keyword: 
IDDQ sensor, CMOS, IDDQ test, bridging fault, 
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Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1605-1608
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Verification of VLSI)
Category: 
Keyword: 
synthesis for testability, redundancy removal, sequential circuit, undetectable faults, unreachable states, 
 Summary | Full Text:PDF
Testable Static CMOS PLA for IDDQ Testing
Masaki HASHIZUME Hiroshi HOSHIKA Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6  pp. 1488-1495
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
static PLA, testable design, IDDQ test, bridging fault, 
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Heuristic State Reduction Methods of Incompletely Specified Machines Preceding to Satisfy Covering Condition
Masaki HASHIZUME Takeomi TAMESADA Takashi SHIMAMOTO Akio SAKAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6  pp. 1045-1054
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)
Category: VLSI Design Technology and CAD
Keyword: 
incompletely specified machine, maximal compatible set, state reduction, 
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A Practical Functional Test Using Flowchart for Production Testing of Microprocessor Based Sequence Controllers
Masaki HASHIZUME Takeomi TAMESADA Eiji TASAKA Toshihiro KAYAHARA Tomohisa YAMAZOE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 837-841
Type of Manuscript:  Special Section LETTER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequence controller, process flowchart, functional test, microprocessor based circuit, 
 Summary | Full Text:PDF