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IEICE Trans

Koyo NITTA

An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture
Ken NAKAMURA Yuya OMORI Daisuke KOBAYASHI Koyo NITTA Kimikazu SANO Masayuki SATO Hiroe IWASAKI Hiroaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2023/06/01
Vol. E106-C  No. 6  pp. 312-320
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
video coding, HEVC, multi-chip, gem5, cache memory, 
 Summary | Full Text:PDF
A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation
Hiroyuki UZAWA Kazuhiko TERADA Koyo NITTA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2021/05/01
Vol. E104-B  No. 5  pp. 481-489
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission for Communications
Keyword: 
power reduction, frame buffer, PON, ONU, 
 Summary | Full Text:PDF
Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems
Saki HATTA Nobuyuki TANAKA Hiroyuki UZAWA Koyo NITTA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2021/03/01
Vol. E104-B  No. 3  pp. 277-285
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission for Communications
Keyword: 
passive optical network, OLT, protocol processing, flexible network, programmable hardware, 
 Summary | Full Text:PDF
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture
Ken NAKAMURA Daisuke KOBAYASHI Yuya OMORI Tatsuya OSAWA Takayuki ONISHI Koyo NITTA Hiroe IWASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 77-84
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
HEVC, decoder, high frame rate, temporal scalability, 
 Summary | Full Text:PDF
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2020/01/01
Vol. E103-B  No. 1  pp. 11-19
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
Keyword: 
service function chaining, real-time image processing, packet-reordering circuit, CPU-FPGA architecture, 
 Summary | Full Text:PDF
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures
Koyo NITTA Hiroe IWASAKI Takayuki ONISHI Takashi SANO Atsushi SAGATA Yasuyuki NAKAJIMA Minoru INAMORI Ryuichi TANIDA Atsushi SHIMIZU Ken NAKAMURA Mitsuo IKEDA Jiro NAGANUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 432-440
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
H.264/AVC, encoder, MPSoC, ME/MC, and HDTV, 
 Summary | Full Text:PDF
Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder
Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/03/01
Vol. E84-D  No. 3  pp. 317-325
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
motion estimation and compensation, scene-adaptive algorithm, MPEG-2 video encoder, hardware architecture, SIMD, 
 Summary | Full Text:PDF
Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
Mitsuo IKEDA Toshio KONDO Koyo NITTA Kazuhito SUGURI Takeshi YOSHITOME Toshihiro MINAMI Jiro NAGANUMA Takeshi OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2  pp. 170-178
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MPEG-2, video signal processing, embedded system LSI, hardware/software co-design, picture coding, 
 Summary | Full Text:PDF
Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses
Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4  pp. 663-669
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computational complexity, Boolean function, ordered binary decision diagram, satisfiability, combinational circuit, cutwidth, sum-of-product form, zero-suppressed binary decision diagrams (BDD), ternary decision diagram, 
 Summary | Full Text:PDF