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Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA
IEICE TRANSACTIONS on Communications
Publication Date: 2020/01/01
Online ISSN: 1745-1345
Type of Manuscript: Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
service function chaining, real-time image processing, packet-reordering circuit, CPU-FPGA architecture,
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Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.