Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder

Koyo NITTA  Toshihiro MINAMI  Toshio KONDO  Takeshi OGURA  

IEICE TRANSACTIONS on Information and Systems   Vol.E84-D   No.3   pp.317-325
Publication Date: 2001/03/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
motion estimation and compensation,  scene-adaptive algorithm,  MPEG-2 video encoder,  hardware architecture,  SIMD,  

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This paper describes a unique motion estimation and compensation (ME/MC) hardware architecture for a scene-adaptive algorithm. By statistically analyzing the characteristics of the scene being encoded and controlling the encoding parameters according to the scene, the quality of the decoded image can be enhanced. The most significant feature of the architecture is that the two modules for ME/MC can work independently. Since a time interval can be inserted between the operations of the two modules, a scene-adaptive algorithm can be implemented in the architecture. The ME/MC architecture is loaded on a single-chip MPEG-2 video encoder.