For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder
Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/03/01
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
motion estimation and compensation, scene-adaptive algorithm, MPEG-2 video encoder, hardware architecture, SIMD,
Full Text: PDF>>
This paper describes a unique motion estimation and compensation (ME/MC) hardware architecture for a scene-adaptive algorithm. By statistically analyzing the characteristics of the scene being encoded and controlling the encoding parameters according to the scene, the quality of the decoded image can be enhanced. The most significant feature of the architecture is that the two modules for ME/MC can work independently. Since a time interval can be inserted between the operations of the two modules, a scene-adaptive algorithm can be implemented in the architecture. The ME/MC architecture is loaded on a single-chip MPEG-2 video encoder.