Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI

Mitsuo IKEDA  Toshio KONDO  Koyo NITTA  Kazuhito SUGURI  Takeshi YOSHITOME  Toshihiro MINAMI  Jiro NAGANUMA  Takeshi OGURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.2   pp.170-178
Publication Date: 2000/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MPEG-2,  video signal processing,  embedded system LSI,  hardware/software co-design,  picture coding,  

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Summary: 
This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.