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IEICE Trans

Kimihiro YAMAKOSHI

Experimental 5-Tb/s Packet-by-Packet Wavelength Switching System Using 2.5 -Gb/s 8-λ WDM Links
Kimihiro YAMAKOSHI Nobuaki MATSUURA Kohei NAKAI Eiji OKI Naoaki YAMANAKA Takaharu OHYAMA Yuji AKAHORI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/07/01
Vol. E85-B  No. 7  pp. 1293-1301
Type of Manuscript:  PAPER
Category: Switching
Keyword: 
packet, switch, WDM, AWG, 
 Summary | Full Text:PDF
A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7  pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, 
 Summary | Full Text:PDF
A New Routing Method Considering Neighboring-Wire Capacitance Constraints
Takumi WATANABE Kimihiro YAMAKOSHI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2679-2687
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routing, wire capacitance, deep-submicron design, CAD, VLSI, 
 Summary | Full Text:PDF
A 40-Gb/s 88 ATM Switch LSI Using 0. 25-µmCMOS/SIMOX
Yusuke OHTOMO Sadayuki YASUDA Masafumi NOGAWA Jun-ichi INOUE Kimihiro YAMAKOSHI Hirotoshi SAWADA Masayuki INO Shigeki HINO Yasuhiro SATO Yuichiro TAKEI Takumi WATANABE Ken TAKEYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 737-745
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: Network
Keyword: 
SOI, CMOS, ATM, high-speed, 
 Summary | Full Text:PDF
An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
Takumi WATANABE Yusuke OHTOMO Kimihiro YAMAKOSHI Yuichiro TAKEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4  pp. 677-684
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routing methodology, maze router, layout, CAD, VLSI, 
 Summary | Full Text:PDF
A Clock Distribution Technique with an Automatic Skew Compensation Circuit
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Vol. E81-C  No. 2  pp. 277-283
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock skew, clock distribution, compensation, variable delay line, CMOS, 
 Summary | Full Text:PDF