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IEICE Trans

Keiji KIMURA

Efficient Memory Protection Method for Large-Scale Host-Enclave Data Transfer on Keystone Enclave
Akihiro SAIKI Keiji KIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2026/06/01
Vol. E109-D  No. 6  pp. 894-910
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
TEE, RISC-V, keystone enclave, PMP, memory sharing, 
 Summary | Full Text:PDF
Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models
Yu OMORI Keiji KIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/05/01
Vol. E104-D  No. 5  pp. 697-708
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
NVMM, emulator, embedded system, behaviour model, Intel Optane DC persistent memory, 
 Summary | Full Text:PDF
Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
Yoshitake OKI Yuto ABE Kazuki YAMAMOTO Kohei YAMAMOTO Tomoya SHIRAKAWA Akimasa YOSHIDA Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 98-109
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
parallelization compiler, local memory management, multicore processor, global address space, data decomposition, 
 Summary | Full Text:PDF
Compiler Software Coherent Control for Embedded High Performance Multicore
Boma A. ADHI Tomoya KASHIMATA Ken TAKAHASHI Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 85-97
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
multicore, software coherence control, parallelizing compiler, shared memory, cache, soft core, 
 Summary | Full Text:PDF
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 663-669
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
heterogeneous, instruction set, MMU, 
 Summary | Full Text:PDF
Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki SHIKANO Jun SHIRAKO Yasutaka WADA Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 432-439
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
chip multiprocessor, parallelizing compiler, frequency and voltage control, 
 Summary | Full Text:PDF
Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture
Keiji KIMURA Takeshi KODAKA Motoki OBATA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 570-579
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
chip multiprocessor, multigrain parallel processing, parallelizing compiler, 
 Summary | Full Text:PDF