Keiji KIMURA


Compiler Software Coherent Control for Embedded High Performance Multicore
Boma A. ADHI Tomoya KASHIMATA Ken TAKAHASHI Keiji KIMURA Hironori KASAHARA 
Publication:   
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 85-97
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
multicoresoftware coherence controlparallelizing compilershared memorycachesoft core
 Summary | Full Text:PDF

Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler
Yoshitake OKI Yuto ABE Kazuki YAMAMOTO Kohei YAMAMOTO Tomoya SHIRAKAWA Akimasa YOSHIDA Keiji KIMURA Hironori KASAHARA 
Publication:   
Publication Date: 2020/03/01
Vol. E103-C  No. 3  pp. 98-109
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
parallelization compilerlocal memory managementmulticore processorglobal address spacedata decomposition
 Summary | Full Text:PDF

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
Osamu NISHII Yoichi YUYAMA Masayuki ITO Yoshikazu KIYOSHIGE Yusuke NITTA Makoto ISHIKAWA Tetsuya YAMADA Junichi MIYAKOSHI Yasutaka WADA Keiji KIMURA Hironori KASAHARA Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 663-669
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
heterogeneousinstruction setMMU
 Summary | Full Text:PDF

Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki SHIKANO Jun SHIRAKO Yasutaka WADA Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4  pp. 432-439
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
chip multiprocessorparallelizing compilerfrequency and voltage control
 Summary | Full Text:PDF

Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture
Keiji KIMURA Takeshi KODAKA Motoki OBATA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 570-579
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
chip multiprocessormultigrain parallel processingparallelizing compiler
 Summary | Full Text:PDF