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IEICE Trans

Kazuteru NAMBA

6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage
Ji WU Ruoxi YU Kazuteru NAMBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2024/09/01
Vol. E107-D  No. 9  pp. 1278-1280
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
neural network, SRAM, bit error rate (BER), low power consumption, AI chips, 
 Summary | Full Text:PDF
Complete Double Node Upset Tolerant Latch Using C-Element
Yuta YAMAMOTO Kazuteru NAMBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/10/01
Vol. E103-D  No. 10  pp. 2125-2132
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
single event upset (SEU), double node upset (DNU), soft error, C-element, 
 Summary | Full Text:PDF
Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge
Kazuteru NAMBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2020/04/01
Vol. E103-D  No. 4  pp. 892-895
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
soft error, DICE (the dual interlocked storage cell), master-slave flip-flop, clock edge, 
 Summary | Full Text:PDF
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10  pp. 2719-2729
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defects, fault coverage, segmented scan, control point, observation point, 
 Summary | Full Text:PDF
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3  pp. 533-540
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defects, test compaction, test application time, test data volume, on-chip delay measurement, 
 Summary | Full Text:PDF
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
Kazuteru NAMBA Nobuhide TAKASHINA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1613-1623
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Test and Verification
Keyword: 
small delay defects, delay measurement, DVMC (delay value measurement circuit), FPGA (field programmable gate array), global routing resource, 
 Summary | Full Text:PDF
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5  pp. 1219-1222
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
small delay faults, test coverage, flip-flop, clock pulse, 
 Summary | Full Text:PDF
Construction of BILBO FF with Soft-Error-Tolerant Capability
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/05/01
Vol. E94-D  No. 5  pp. 1045-1050
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft-error-tolerance, DFT (design for test), BISER (built-in soft-error resilience), BILBO (built-in logic block observer), reconfigurable C-element, 
 Summary | Full Text:PDF
Single-Event-Upset Tolerant RS Flip-Flop with Small Area
Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12  pp. 3407-3409
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
soft error, single-event-upset (SEU) tolerance, reset-set flip-flop (RS-FF), interlocking feedback loop, 
 Summary | Full Text:PDF
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuit, path delay fault, testability, functional sensitizability, over-testing, 
 Summary | Full Text:PDF
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
Shuangyu RUAN Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/08/01
Vol. E92-D  No. 8  pp. 1534-1541
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
soft error, wide pulse, flip-flop, C-element, delay element, 
 Summary | Full Text:PDF
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3  pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
dual circuits, master and slave scan paths, delay fault testing, concurrent error detection, DFT, 
 Summary | Full Text:PDF
Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuits, design for testability, delay fault testing, scan design, set-reset operation, 
 Summary | Full Text:PDF
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 269-282
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compression, statistical coding, run-length coding, delay fault testing, two-pattern testing, scan testing, 
 Summary | Full Text:PDF
Redundant Design for Wallace Multiplier
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/09/01
Vol. E89-D  No. 9  pp. 2512-2524
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Wallace multiplier, bit-slice reconfiguration redundant design, defect-tolerance, yield, 
 Summary | Full Text:PDF
Proposal of Testable Multi-Context FPGA Architecture
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5  pp. 1687-1693
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-context FPGA, single stuck-at fault, design for testability, 
 Summary | Full Text:PDF
Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12  pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testing, delay fault testing, scan design, enhanced scan, 
 Summary | Full Text:PDF
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9  pp. 2135-2142
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testing, adjacency test, deterministic test generation, BIST, 
 Summary | Full Text:PDF
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities
Kazuteru NAMBA Eiji FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1426-1430
Type of Manuscript:  LETTER
Category: Coding Theory
Keyword: 
unequal error protection code, two-level UEP codes, burst error correcting Fire code, 
 Summary | Full Text:PDF