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Vol.E75-A No.10
pp.1255-1262
Special SectionPAPER
Parallel Binary Decision Diagram Manipulation
Shinji KIMURA, Tsutomu IGAKI, Hiromasa HANEDA, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1263-1271
Special SectionPAPER
A Logic Diagnosis Technique for Multiple Output Circuit
Naoaki SUGANUMA, Nobuto UEDA, Masahiro TOMITA, Kotaro HIRANO, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1272-1279
Special SectionPAPER
An Efficient Hypergraph Bisection Algorithm for Partitioning VLSI Circuits
Yoko KAMIDOI, Shin'ichi WAKABAYASHI, Noriyoshi YOSHIDA, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1280-1285
Special SectionPAPER
A Fuzzy-Theoretic Timing Driven Placement Method
Ze Cang GU, Shoichiro YAMADA, Kunio FUKUNAGA, Shojiro YONEDA, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1286-1293
Special SectionPAPER
Placement and Routing Algorithms for One-Dimensional CMOS Layout Synthesis with Physical Constraints
Katsunori TANI, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1294-1300
Special SectionPAPER
A Hierarchical Multi-Layer Global Router
Masayuki HAYASHI, Hiroyoshi YAMAZAKI, Shuji TSUKIYAMA, Nobuyuki NISHIGUCHI, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1301-1305
Special SectionPAPER
Switched Capacitor and Active-RC Filter Layout Using a Parameterizable Generator
Takao KANEKO, Yukio AKAZAWA, Mitsuyoshi NAGATANI, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1306-1314
Special SectionPAPER
An Automatic Layout Generator for Bipolar Analog Modules
Takao ONOYE, Akihisa YAMADA, Itthichai ARUNGSRISANGCHAI, Masakazu TANAKA, Isao SHIRAKAWA, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1315-1316
FOREWORD
FOREWORD
Sadatoshi KUMAGAI, |
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Summary | Full Text:PDF | |
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Vol.E75-A No.10
pp.1317-1325
INVITED PAPER
Net-Oriented Analysis and Design
Shinichi HONIDEN, Naoshi UCHIHIRA, |
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Summary | Full Text:PDF | |
| Current List: 40871 - 40880
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