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Vol.E76-C No.7
pp.1159-1166 Special SectionPAPER
Neural Networks and Chips Hardware Architecture for Kohonen Network Hidetoshi ONODERA, Kiyoshi TAKESHITA, Keikichi TAMARU, |
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Vol.E76-C No.7
pp.1167-1173 Special SectionPAPER
Neural Networks and Chips Deterministic Boltzmann Machine Learning Improved for Analog LSI Implementation Takashi MORIE, Yoshihito AMEMIYA, |
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Vol.E76-C No.7
pp.1174-1181 Special SectionPAPER
Neural Networks and Chips Parallel VLSI Architecture for Multi-Layer Self-Organizing Cellular Network Yoshikazu MIYANAGA, Koji TOCHINAI, |
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Vol.E76-C No.7
pp.1182-1190 Special SectionPAPER
Neural Networks and Chips Development and Fabrication of Digital Neural Network WSIs Minoru FUJITA, Yasushi KOBAYASHI, Kenji SHIOZAWA, Takahiko TAKAHASHI, Fumio MIZUNO, Hajime HAYAKAWA, Makoto KATO, Shigeki MORI, Tetsuro KASE, Minoru YAMADA, |
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Vol.E76-C No.7
pp.1191-1196 Special SectionPAPER
Neural Networks and Chips A Digital Neural Network Coprocessor with a Dynamically Reconfigurable Pipeline Architecture Takayuki MORISHITA, Youichi TAMURA, Takami SATONAKA, Atsuo INOUE, Shin-ichi KATSU, Tatsuo OTSUKI, |
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Vol.E76-C No.7
pp.1197-1205 Special SectionPAPER
Neural Networks and Chips A Programmable Parallel Digital Neurocomputer Yoshiyuki SHIMOKAWA, Yutaka FUWA, Naruhiko ARAMAKI, |
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Vol.E76-C No.7
pp.1206-1214 Special SectionPAPER
Neural Networks and Chips The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips Takao WATANABE, Masakazu AOKI, Katsutaka KIMURA, Takeshi SAKATA, Kiyoo ITOH, |
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Vol.E76-C No.7
pp.1215-1223 PAPER
Opto-Electronics 8 8 Optical Matrix Switch Using Silica-Based Planar Lightwave Circuits Masayuki OKUNO, Akio SUGITA, Tohru MATSUNAGA, Masao KAWACHI, Yasuji OHMORI, Katsumi KATOH, |
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Vol.E76-D No.7
pp.737-738 FOREWORD
FOREWORD Kozo KINOSHITA, |
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Vol.E76-D No.7
pp.739-746 Special SectionPAPER
Synthesis of Testable Sequential Circuits with Reduced Checking Sequences Satoshi SHIBATANI, Kozo KINOSHITA, |
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