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Vol.E76-D No.9
pp.1047-1054
Special SectionPAPER
High-Level Design
High-Level Synthesis Design at NTT Systems Labs
Yukihiro NAKAMURA, Kiyoshi OGURI, Akira NAGOYA, Mitsuteru YUKISHITA, Ryo NOMURA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1055-1065
Special SectionPAPER
Hardware Design Languages
VHDL, Verilog-HDL, and UDL/I-Feature Description and Analysis
P. N. SANKARSHANAN, Hideaki KOBAYASHI, Pankaj KUKKAL, Hiroyuki KANBARA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1066-1074
Special SectionPAPER
Hardware Design Languages
A Language for Designing Module Generators
Vasily G. MOSHNYAGA, Keikichi TAMARU, Hiroto YASUURA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1075-1084
Special SectionPAPER
Logic Synthesis
Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis
Kuo-Hua WANG, Ting-Ting HWANG, Cheng CHEN, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1085-1092
Special SectionPAPER
Logic Synthesis
Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Nagisa ISHIURA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1093-1101
Special SectionPAPER
Logic Synthesis
Coherent Optimisation Strategies for Multilevel Synthesis
Khalid SAKOUTI, Pierre ABOUZEID, Michel CRASTES, Thierry BESSON, Jerome FRON, Gabrièle SAUCIER, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1102-1113
Special SectionPAPER
Logic Synthesis
Network Resynthesis Algorithms for Delay Minimization
Kuang-Chien CHEN, Masahiro FUJITA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1114-1120
Special SectionPAPER
Test
Enhanced Unique Sensitization for Efficient Test Generation
Yusuke MATSUNAGA, Masahiro FUJITA, |
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Summary | Full Text:PDF | |
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Vol.E76-D No.9
pp.1121-1127
Special SectionPAPER
Test
Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI, Nagisa ISHIURA, Shuzo YAJIMA, |
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Summary | Full Text:PDF | |
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Vol.E76-A No.8
pp.1281-1282
FOREWORD
FOREWORD
Tsuyoshi TAKEBE, |
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Summary | Full Text:PDF | |
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