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Vol.E79-D No.4
pp.385-387
LETTER
Computer Hardware and Design
A Supplementary Scheme for Reducing Cache Access Time
Jong-Hong BAE, Chong-Min KYUNG, |
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Vol.E79-D No.4
pp.388-391
LETTER
Image Processing,Computer Graphics and Pattern Recognition
One Simple Approach for Radial Symmetrical Point Detection
Hiroshi KONDO, Shuji TUTUMI, Satoshi MIKURIYA, |
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Vol.E79-A No.3
pp.273-274
FOREWORD
FOREWORD
Hiroshi TANIMOTO, Hisashi YAMADA, |
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Vol.E79-A No.3
pp.275-282
Special SectionPAPER
High-Speed Adaptive Noise Canceller with Parallel Block Structure
Kiyoyasu MARUYAMA, Chawalit BENJANGKAPRASERT, Nobuaki TAKAHASHI, Tsuyoshi TAKEBE, |
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Vol.E79-A No.3
pp.283-290
Special SectionPAPER
Design of FIR Digital Filters Using Estimates of Error Function over CSD Coefficient Space
Mitsuhiko YAGYU, Akinori NISHIHARA, Nobuo FUJII, |
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Vol.E79-A No.3
pp.291-296
Special SectionPAPER
Filter Bank Implementation of the Shift Operation in Orthonormal Wavelet Bases
Achim GOTTSCHEBER, Akinori NISHIHARA, |
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Vol.E79-A No.3
pp.297-303
Special SectionPAPER
Network Reflection and Transmission Coefficients for the Interconnection of Multi-Port Multi-Line Junction Networks
Iwata SAKAGAMI, |
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Vol.E79-A No.3
pp.304-311
Special SectionPAPER
Estimation of short-Circuit Power Dissipation for Static CMOS Gates
Akio HIRATA, Hidetoshi ONODERA, Keikichi TAMARU, |
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Vol.E79-A No.3
pp.312-320
Special SectionPAPER
Power and Area Minimization by Reorganizing CMOS Complex-Gates
Masayoshi TACHIBANA, Sachiko KUROSAWA, Reiko NOJIMA, Naohito KOJIMA, Masaaki YAMADA, Takashi MITSUHASHI, Nobuyuki GOTO, |
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Vol.E79-A No.3
pp.321-329
Special SectionPAPER
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, |
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| Current List: 37731 - 37740
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