|
Vol.E81-A No.12
pp.2529-2537
Special SectionPAPER
Logic Synthesis
An Efficient Method for Finding an Optimal Bi-Decomposition
Shigeru YAMASHITA, Hiroshi SAWADA, Akira NAGOYA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2538-2544
Special SectionPAPER
Logic Synthesis
Restructuring Logic Representations with Simple Disjunctive Decompositions
Hiroshi SAWADA, Shigeru YAMASHITA, Akira NAGOYA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2545-2553
Special SectionPAPER
Logic Synthesis
Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions
Hafiz Md. HASAN BABU, Tsutomu SASAO, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2554-2562
Special SectionPAPER
Logic Synthesis
Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA, Shigeru YAMASHITA, Yahiko KAMBAYASHI, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2563-2575
Special SectionPAPER
High-level Synthesis
A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration
Nozomu TOGAWA, Takafumi HISAKI, Masao YANAGISAWA, Tatsuo OHTSUKI, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2576-2584
Special SectionPAPER
High-level Synthesis
Module Selection Using Manufacturing Information
Hiroyuki TOMIYAMA, Hiroto YASUURA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2585-2594
Special SectionPAPER
Design Reuse
Program Slicing on VHDL Descriptions and Its Evaluation
Shigeru ICHINOSE, Mizuho IWAIHARA, Hiroto YASUURA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2595-2604
Special SectionPAPER
Co-design
Language and Compiler for Optimizing Datapath Widths of Embedded Systems
Akihiko INOUE, Hiroyuki TOMIYAMA, Takanori OKUMA, Hiroyuki KANBARA, Hiroto YASUURA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2605-2611
Special SectionPAPER
Co-design
Efficient and Flexible Cosimulation Environment for DSP Applications
Wonyong SUNG, Soonhoi HA, |
|
Summary | Full Text:PDF | |
|
Vol.E81-A No.12
pp.2612-2620
Special SectionPAPER
Co-design
An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes
Nguye n Ngoc BINH, Masaharu IMAI, Yoshinori TAKEUCHI, |
|
Summary | Full Text:PDF | |
|
Current List: 34811 - 34820
|