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Vol.E82-D No.1
pp.309-317
PAPER
Artificial Intelligence and Cognitive Science
Genetic Algorithms for Adaptive Planning of Path and Trajectory of a Mobile Robot in 2D Terrains
Kazuo SUGIHARA, John SMITH, |
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Summary | Full Text:PDF | |
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Vol.E82-D No.1
pp.318-325
PAPER
Bio-Cybernetics and Neurocomputing
Fully-Connected Neural Network Model of Associative Memory as a Test Function of Evolutionary Computations
Akira IMADA, Keijiro ARAKI, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2475-2475
FOREWORD
FOREWORD
Masaharu IMAI, Hitoshi KITAZAWA, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2476-2484
Special SectionPAPER
Layout Optimization
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE, Shin'ichi WAKABAYASHI, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2485-2491
Special SectionPAPER
Layout Optimization
On Improved FPGA Greedy Routing Architectures
Yu-Liang WU, Douglas CHANG, Malgorzata MAREK-SADOWSKA, Shuji TSUKIYAMA, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2492-2500
Special SectionPAPER
Layout Optimization
Layout Abstraction and Technology Retargeting for Leaf Cells
Masahiro FUKUI, Noriko SHINOMIYA, Syunji SAIKA, Toshiro AKINO, Shigeo KUNINOBU, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2501-2508
Special SectionPAPER
Transistor-level Circuit Analysis, Design and Verification
Efficient Curve Fitting Technique for Analysis of Interconnect Networks with Frequency-Dependent Parameters
Yuichi TANJI, Yoshifumi NISHIO, Takashi SHIMAMOTO, Akio USHIDA, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2509-2514
Special SectionPAPER
Transistor-level Circuit Analysis, Design and Verification
Dual-Loop Digital PLL Design for Adaptive Clock Recovery
Tae Hun KIM, Beomsup KIM, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2515-2520
Special SectionPAPER
Timing Verification and Optimization
Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA, Shinji KIMURA, Kazuyoshi TAKAGI, Katsumasa WATANABE, |
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Summary | Full Text:PDF | |
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Vol.E81-A No.12
pp.2521-2528
Special SectionPAPER
Timing Verification and Optimization
Design Optimization by Using Flexible Pipelined Modules
Masahiro FUKUI, Masakazu TANAKA, Masaharu IMAI, |
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Summary | Full Text:PDF | |
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Current List: 34801 - 34810
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