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Vol.E83-A No.12
pp.2474-2487
Special SectionPAPER
Co-design and High-level Synthesis
Multicriteria Codesign Optimization for Embedded Multimedia Communication System
I-Horng JENG, Feipei LAI, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2488-2497
Special SectionPAPER
Co-design and High-level Synthesis
Intrinsic Evolution for Synthesis of Fault-Recoverable Circuit
Tae-Suh PARK, Chong-Ho LEE, Duck-Jin CHUNG, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2498-2504
Special SectionPAPER
Logic Synthesis
Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU, Tsutomu SASAO, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2505-2512
Special SectionPAPER
Logic Synthesis
An Algorithm for Generating Generic BDDs
Tetsushi KATAYAMA, Hiroyuki OCHI, Takao TSUDA, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2513-2519
Special SectionPAPER
Logic Synthesis
Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications
Hiroshi SAWADA, Shigeru YAMASHITA, Akira NAGOYA, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2520-2527
Special SectionPAPER
Logic Synthesis
Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
Qiang ZHU, Yusuke MATSUNAGA, Shinji KIMURA, Katsumasa WATANABE, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2528-2537
Special SectionPAPER
Logic Synthesis
Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD, Etsuko OKUSHI, Mitsuhiro YASUDA, Hisao KOIZUMI, Katsuhiko SEO, Hiroto YASUURA, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2538-2544
Special SectionPAPER
Logic Synthesis
Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture
Tomonori IZUMI, Ryuji KAN, Yukihiro NAKAMURA, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2545-2551
Special SectionPAPER
Performance Optimization
Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
Hsien-Ho CHUANG, Jing-Yang JOU, C. Bernard SHUNG, |
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Summary | Full Text:PDF | |
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Vol.E83-A No.12
pp.2552-2557
Special SectionPAPER
Performance Optimization
Clock Schedule Design for Minimum Realization Cost
Tomoyuki YODA, Atsushi TAKAHASHI, |
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Summary | Full Text:PDF | |
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Current List: 32471 - 32480
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