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IEICE Trans

Keyword : wrapper design

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 807-814
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-clock domain, wrapper design, SoC, embedded core test, test scheduling, 
 Summary | Full Text:PDF
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores
Yinhe HAN Yu HU Xiaowei LI Huawei LI Anshuman CHANDRA Xiaoqing WEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9 ; pp. 2126-2134
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SOC testing, wrapper design, scan slices, overlapping, 
 Summary | Full Text:PDF