Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores

Yinhe HAN
Xiaowei LI
Huawei LI
Anshuman CHANDRA
Xiaoqing WEN

IEICE TRANSACTIONS on Information and Systems   Vol.E88-D    No.9    pp.2126-2134
Publication Date: 2005/09/01
Online ISSN: 
DOI: 10.1093/ietisy/e88-d.9.2126
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
SOC testing,  wrapper design,  scan slices,  overlapping,  

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Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and internal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.