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IEICE Trans

Keyword : redundancy removal

Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1605-1608
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Verification of VLSI)
Category: 
Keyword: 
synthesis for testability, redundancy removal, sequential circuit, undetectable faults, unreachable states, 
 Summary | Full Text:PDF
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 861-867
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
retiming, logic synthesis, redundancy removal, test synthesis, 
 Summary | Full Text:PDF