A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework Yukihide KOHIRAAtsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-ANo. 10 ;
pp. 3030-3037 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: register relocation, retiming, clock scheduling, general-synchronous framework,
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization Yukihide KOHIRAAtsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-ANo. 4 ;
pp. 800-807 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: register relocation, retiming, clock period minimization, generalized synchronous framework,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-ANo. 12 ;
pp. 3100-3108 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: multiple voltage scheduling, low-power circuit, loop shrinking, retiming, unfolding, high-level synthesis,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-DNo. 7 ;
pp. 861-867 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: retiming, logic synthesis, redundancy removal, test synthesis,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/06/25 Vol. E77-ANo. 6 ;
pp. 977-984 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93)) Category: Analog Circuits and Signal Processing Keyword: PLL, jitter, time-domain simulation, phase detector, NRZ, retiming,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-ANo. 10 ;
pp. 1191-1201 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, optimization, retiming, iteration bound, scheduling,
