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IEICE Trans

Keyword : partial scan design method

Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops
Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 660-667
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testability, partial scan design method, n-fold line-up structure, pure load/hold FF, 
 Summary | Full Text:PDF