Mitsuyasu OHTA

Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2722-2730
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
DFT strategies, full scan design methods, partial scan design methods, test point insertions, test application time, 
 Summary | Full Text:PDF
Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops
Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 660-667
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testability, partial scan design method, n-fold line-up structure, pure load/hold FF, 
 Summary | Full Text:PDF
A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1436-1442
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword: 
design for testability, partial scan design, register-transfer level, automatic test-pattern generation, ESDA, 
 Summary | Full Text:PDF