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IEICE Trans

Keyword : microarchitecture

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA
Reoma MATSUO Toru KOIZUMI Hidetsugu IRIE Shuichi SAKAI Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/06/01
Vol. E108-D  No. 6 ; pp. 558-569
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
GPU, microarchitecture, instruction-level parallelism, out-of-order execution, energy efficiency, 
 Summary | Full Text:PDF
An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation point, sampling simulation, microarchitecture, processor architecture, simulation, computer architecture, 
 Summary | Full Text:PDF
Using Cacheline Reuse Characteristics for Prefetcher Throttling
Hidetsugu IRIE Takefumi MIYOSHI Goki HONJO Kei HIRAKI Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 2928-2938
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
microarchitecture, cache, prefetch, 
 Summary | Full Text:PDF
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
Yusuke TANAKA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12 ; pp. 3294-3305
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microarchitecture, microprocessor, instruction pre-execution, value prediction, register file, 
 Summary | Full Text:PDF
Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
Kazunaga HYODO Kengo IWAMOTO Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/11/01
Vol. E92-D  No. 11 ; pp. 2186-2195
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
microarchitecture, microprocessor, instruction pre-execution, low power, 
 Summary | Full Text:PDF
A Low-Power Branch Predictor for Embedded Processors
Sung Woo CHUNG Gi Ho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/09/01
Vol. E87-D  No. 9 ; pp. 2253-2257
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
microarchitecture, branch predictor, global predictor, gshare, low-power design, 
 Summary | Full Text:PDF
A Low-Power Tournament Branch Predictor
Sung Woo CHUNG Gi Ho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7 ; pp. 1962-1964
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
microarchitecture, tournament branch predictor, local history, global history, low-power design, memory compiler, 
 Summary | Full Text:PDF
Design Development of SPARC64 V Microprocessor
Mariko SAKAMOTO Akira KATSUNO Aiichiro INOUE Takeo ASAKAWA Kuniki MORITA Tsuyoshi MOTOKURUMADA Yasunori KIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10 ; pp. 1955-1965
Type of Manuscript:  INVITED PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
microprocessor, microarchitecture, UNIX server, enterprise server, software performance simulator, 
 Summary | Full Text:PDF