Design Development of SPARC64 V Microprocessor

Mariko SAKAMOTO  Akira KATSUNO  Aiichiro INOUE  Takeo ASAKAWA  Kuniki MORITA  Tsuyoshi MOTOKURUMADA  Yasunori KIMURA  

IEICE TRANSACTIONS on Information and Systems   Vol.E86-D   No.10   pp.1955-1965
Publication Date: 2003/10/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: INVITED PAPER (Special Issue on Development of Advanced Computer Systems)
microprocessor,  microarchitecture,  UNIX server,  enterprise server,  software performance simulator,  

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We developed a SPARC-V9 processor, the SPARC64 V. It has an operating frequency of 1.35 GHz and contains 191 million transistors fabricated using 0.13-µm CMOS technology with eight-layer copper metallization. SPECjbb2000 (CPU# 32) is 492683, highest on the market and 42% higher than the next highest system. SPEC CPU2000 performance is 858 for SPECint and 1228 for SPECfp. The processor is designed to provide the high system performance and high reliability required of enterprise server systems. It is also designed to address the performance requirements of high-performance computing. During our development of several generations of mainframe processors, we conducted many related experiments, and obtained enterprise server system (EPS) development skills, an understanding of EPS workload characteristics, and technology that provides high reliability, availability, and serviceability. We used those as bases of the new processor development. The approach quite effectively moves beyond differences between mainframe and SPARC systems. At the beginning of development and before the start of hardware design, we developed a software performance simulator so we could understand the performance impacts of created specifications, thereby enabling us to make appropriate decisions about hardware design. We took this approach to solve performance problems before tape-out and avoid spending additional time on design update and physical machine reconstruction. We were successful, completing the high-performance processor development on schedule and in a short time. This paper describes the SPARC64 V microprocessor and performance analyses for development of its design.