A Low-Power Tournament Branch Predictor

Sung Woo CHUNG  Gi Ho PARK  Sung Bae PARK  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E87-D   No.7   pp.1962-1964
Publication Date: 2004/07/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer Systems
Keyword: 
microarchitecture,  tournament branch predictor,  local history,  global history,  low-power design,  memory compiler,  

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Summary: 
This letter proposes a low-power tournament branch predictor, in which the number of accesses to the branch predictors (local predictor or global predictor) is reduced. Analysis results with Samsung Memory Compiler show that the proposed branch predictor reduces the power consumption by 24-45%, compared to the conventional tournament branch predictor, not requiring any additional storage arrays, not incurring any additional delay and never harming accuracy.