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IEICE Trans

Keyword : loop mapping

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
Bing XU Shouyi YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 243-251
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
loop mapping, software pipelining, Dual-VDD, low power, Graph Minor, 
 Summary | Full Text:PDF