Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-DNo. 2 ;
pp. 243-251 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: loop mapping, software pipelining, Dual-VDD, low power, Graph Minor,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-ANo. 6 ;
pp. 1464-1475 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: software pipelining, interconnect delay, high level synthesis, scheduling, performance,