Keyword : software pipelining

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
Bing XU Shouyi YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 243-251
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
loop mapping, software pipelining, Dual-VDD, low power, Graph Minor, 
 Summary | Full Text:PDF
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
Shanghua GAO Hiroaki YOSHIDA Kenshu SETO Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1464-1475
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
software pipelining, interconnect delay, high level synthesis, scheduling, performance, 
 Summary | Full Text:PDF
Resource-Optimal Software Pipelining Using Flow Graphs
Dirk FIMMEL Jan MULLER Renate MERKER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/09/01
Vol. E86-D  No. 9 ; pp. 1560-1568
Type of Manuscript:  INVITED PAPER (Special Issue on Parallel and Distributed Computing, Applications and Technologies)
Category: Software Systems and Technologies
Keyword: 
software pipelining, instruction level parallelism, integer linear programming, resource constraints, heterogeneous architectures, 
 Summary | Full Text:PDF