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IEICE Trans

Keyword : automatic test-pattern generation

A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1436-1442
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword: 
design for testability, partial scan design, register-transfer level, automatic test-pattern generation, ESDA, 
 Summary | Full Text:PDF