Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D
No. 10 ;
pp. 1436-1442
Type of Manuscript:
Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword:
design for testability, partial scan design, register-transfer level, automatic test-pattern generation, ESDA, |
