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| Keyword : VLSI design
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Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit
Myungchul YOON | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12 ;
pp. 2357-2363
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
low-power design, VLSI design, bus-invert coding, performance analysis, | | | Summary | Full Text:PDF | |
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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping HU Tiefeng XU Hong LI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D
No. 7 ;
pp. 1479-1485
Type of Manuscript:
Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword:
register file, low power, adiabatic logic, VLSI design, | | | Summary | Full Text:PDF | |
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A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG Chien-Jyh LIU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12 ;
pp. 3109-3115
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
low-power, architecture, VLSI design, FSM, gating, synthesis, | | | Summary | Full Text:PDF | |
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Wire Length Expressions for Analytical Placement Approach
Shoichiro YAMADA Masahiro KASAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A
No. 4 ;
pp. 716-718
Type of Manuscript:
LETTER
Category: Computer Aided Design (CAD)
Keyword:
placement, CAD, VLSI design, | | | Summary | Full Text:PDF | |
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