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VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/12/01
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: VLSI Systems
discrete wavelet transform, lifting scheme, VLSI design, multimedia applications,
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In this paper, a VLSI architecture for lifting-based discrete wavelet transform (LDWT) is presented. Our architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Due to the regular and flexible structure of the design, its area is independent of the length of the 1-D input sequence, and its latency is independent of the number of resolution levels. For the computations of analysis process of N-sample 1-D 3-level LDWT, our design takes about N clock cycles and requires 2 multipliers, 4 adders, and 22 registers. It is fabricated with TSMC 0.35-µm cell library and has a die size of 1.21.2 mm2. The power dissipation of the chip is about 0.4 W at the clock rate of 80 MHz.