Sang-Yeol HAN


Efficient Timing Verification of Latch-Synchronized Systems
Sang-Yeol HAN Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9  pp. 1676-1683
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI designsynchronous elementscritical path analysistiming error
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