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IEICE Trans

Keyword : minimum latency

High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1101-1107
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
intelligent integrated systems, high-level synthesis, parallel processing, minimum latency, scheduling, 
 Summary | Full Text:PDF
A Minimum-Latency Linear Array FFT Processor for Robotics
Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/06/25
Vol. E76-D  No. 6 ; pp. 680-688
Type of Manuscript:  PAPER
Category: Speech Processing
Keyword: 
FFT, correlation, robotics, minimum latency, linear array processor, 
 Summary | Full Text:PDF