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High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
intelligent integrated systems, high-level synthesis, parallel processing, minimum latency, scheduling,
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In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.