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IEICE Trans

Keyword : asynchronous architecture

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAs, reconfigurable VLSIs, asynchronous architecture, LEDR (Level-Encoded Dual-Rail) encoding, 
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