Keyword : LEDR (Level-Encoded Dual-Rail) encoding


An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/08/01
Vol. E93-C  No. 8 ; pp. 1338-1348
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
reconfigurable VLSIfield-programmable VLSILEDR (Level-Encoded Dual-Rail) encoding4-phase dual-rail encodingself-timed architecture
 Summary | Full Text:PDF

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAsreconfigurable VLSIsasynchronous architectureLEDR (Level-Encoded Dual-Rail) encoding
 Summary | Full Text:PDF