Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture

Masanori HARIYAMA  Shota ISHIHARA  Michitaka KAMEYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E91-C   No.9   pp.1419-1426
Publication Date: 2008/09/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e91-c.9.1419
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAs,  reconfigurable VLSIs,  asynchronous architecture,  LEDR (Level-Encoded Dual-Rail) encoding,  

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Summary: 
This paper presents a novel asynchronous architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.