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IEICE Trans

Keyword : TLB

A Leakage Efficient Instruction TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8 ; pp. 1565-1574
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage power, TLB, embedded processor, 
 Summary | Full Text:PDF
A Leakage Efficient Data TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1 ; pp. 51-59
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage power, TLB, embedded processor, 
 Summary | Full Text:PDF
Unified Tag Memory Architecture with Snoop Support
Yonghwan LEE Wookyeong JEONG Yongsurk LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1172-1175
Type of Manuscript:  Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Systems and Control
Keyword: 
unified tag, cache tag, TLB, VLSI, 
 Summary | Full Text:PDF
Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2 ; pp. 210-217
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessor, TLB, CAM, 0. 35 µm, CMOS, 
 Summary | Full Text:PDF
A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits
Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 757-762
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
TLB, CAM, low power, fully associative, 
 Summary | Full Text:PDF
Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors
Norio UTSUMI Akifumi NAGAO Tetsuro YOSHIMOTO Ryuichi YAMAGUCHI Jiro MIYAKE Hisakazu EDAMATSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1202-1211
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: RISC Technologies
Keyword: 
performance evaluation, TLB, SPARC, PTC, SPEC, 
 Summary | Full Text:PDF