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IEICE Trans

Keyword : 64 Mbit

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA Toshio TAKESHIMA Hiroshi TAKADA Yoshiaki S. HISAMUNE Kohji KANAMORI Takeshi OKAZAWA Tatsunori MUROTANI Isao SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 825-831
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory, 64 Mbit, multi-bit programming, data register, hierarchical, 
 Summary | Full Text:PDF
A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory
Ken-ichi OYAMA Noriaki KODAMA Hiroki SHIRAI Kenji SAITOH Yosiaki S. HISAMUNE Takeshi OKAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1358-1363
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
flash memory, 64 Mbit, DSA structure, erasing scheme, charge pumping, 
 Summary | Full Text:PDF