Tatsunori MUROTANI


Hierarchical Word-Line Architecture for Large Capacity DRAMs
Tatsunori MUROTANI Tadahiko SUGIBAYASHI Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 550-556
Type of Manuscript:  INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: Memory LSI
Keyword: 
DRAMhierarchical word linepartial subarray activation
 Summary | Full Text:PDF

A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMhierarchical bit-linerefresh
 Summary | Full Text:PDF

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA Toshio TAKESHIMA Hiroshi TAKADA Yoshiaki S. HISAMUNE Kohji KANAMORI Takeshi OKAZAWA Tatsunori MUROTANI Isao SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 825-831
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory64 Mbitmulti-bit programmingdata registerhierarchical
 Summary | Full Text:PDF

Design Rule Relaxation Approach for High-Density DRAMs
Takanori SAEKI Eiichiro KAKEHASHI Hidemitu MORI Hiroki KOGA Kenji NODA Mamoru FUJITA Hiroshi SUGAWARA Kyoichi NAGATA Shozo NISHIMOTO Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3  pp. 406-415
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAMdesign ruleclose packed cell arrayBoosted Dual Word-Line scheme
 Summary | Full Text:PDF