Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-CNo. 4pp. 550-556 Type of Manuscript: INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Memory LSI Keyword: DRAM, hierarchical word line, partial subarray activation,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-CNo. 7pp. 825-831 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: flash memory, 64 Mbit, multi-bit programming, data register, hierarchical,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/03/25 Vol. E77-CNo. 3pp. 406-415 Type of Manuscript: Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies) Category: Device Technology Keyword: DRAM, design rule, close packed cell array, Boosted Dual Word-Line scheme,
