A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory

Ken-ichi OYAMA  Noriaki KODAMA  Hiroki SHIRAI  Kenji SAITOH  Yosiaki S. HISAMUNE  Takeshi OKAZAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.11   pp.1358-1363
Publication Date: 1992/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
flash memory,  64 Mbit,  DSA structure,  erasing scheme,  charge pumping,  

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Summary: 
A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.