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IEICE Trans

Keyword : parallel clock and data recovery

A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications
Hae-Moon SEO Chang-Gene WOO Sang-Won OH Sung-Wook JUNG Pyung CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1720-1727
Type of Manuscript:  PAPER
Category: General Fundamentals and Boundaries
Keyword: 
parallel clock and data recovery, CMOS, optical communications, low power, 
 Summary | Full Text:PDF