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IEICE Trans

Yutaka MASUDA

Optoelectronic Pipeline Architecture of Convolutional RNN for Energy Efficient Inference at the Speed of Light
Chunlu WANG Yutaka MASUDA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2025/06/01
Vol. E108-C  No. 6  pp. 324-333
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips and Systems)
Category: 
Keyword: 
optical neural network, convolutional neural network, recurrent neural network, 
 Summary | Full Text:PDF
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits
Jiaxuan LU Yutaka MASUDA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/03/01
Vol. E107-A  No. 3  pp. 540-548
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Technology and CAD
Keyword: 
approximate computing, importance evaluation, fault injection, 
 Summary | Full Text:PDF
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform
Takumi KOMORI Yutaka MASUDA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/01/01
Vol. E107-A  No. 1  pp. 3-15
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
dynamic voltage scaling, virtual machine monitors, real-time systems, mixed-criticality, embedded software, 
 Summary | Full Text:PDF
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing
Lingxiao HOU Yutaka MASUDA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/03/01
Vol. E106-A  No. 3  pp. 532-541
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
approximate computing, energy-efficient computing, low power design, vector acceleration, single instruction multiple data, 
 Summary | Full Text:PDF
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing
Yutaka MASUDA Yusei HONDA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/03/01
Vol. E106-A  No. 3  pp. 514-522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
approximate computing (AC), coverage-based grey-box fuzzing (CGF), design under verification (DUV) integration, verification, computational quality, 
 Summary | Full Text:PDF
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing
Takumi KOMORI Yutaka MASUDA Jun SHIOMI Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2022/03/01
Vol. E105-A  No. 3  pp. 518-529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB), real-time operating system (RTOS), soft real-time scheduling, 
 Summary | Full Text:PDF
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling
Yutaka MASUDA Jun NAGAYAMA TaiYu CHENG Tohru ISHIHARA Yoichi MOMIYAMA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2022/03/01
Vol. E105-A  No. 3  pp. 509-517
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
critical path isolation, bit-width scaling, voltage over-scaling, approximate computing, 
 Summary | Full Text:PDF
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
TaiYu CHENG Yutaka MASUDA Jun NAGAYAMA Yoichi MOMIYAMA Jun CHEN Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2022/03/01
Vol. E105-A  No. 3  pp. 497-508
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
mode-wise voltage-scaling, activation-aware slack assignment, multi-corner multi-mode, downhill simplex method, 
 Summary | Full Text:PDF
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation
Naoki HATTORI Jun SHIOMI Yutaka MASUDA Tohru ISHIHARA Akihiko SHINYA Masaya NOTOMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2021/11/01
Vol. E104-A  No. 11  pp. 1477-1487
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
neural network, optical circuit, multi-layer perceptron, wavelength division multiplexing, 
 Summary | Full Text:PDF
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop
Yutaka MASUDA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/07/01
Vol. E102-A  No. 7  pp. 867-877
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
adaptive voltage scaling, activation-aware slack assignment, mean time to failure, timing error predictive FF, 
 Summary | Full Text:PDF
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors
Yutaka MASUDA Takao ONOYE Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1452-1463
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
electrical timing error, software-based error detection, EDM transformation, error detection, 
 Summary | Full Text:PDF