IEICE Trans

Tohru ISHIHARA

Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing Takumi KOMORI Yutaka MASUDA Jun SHIOMI Tohru ISHIHARA
Publication: Publication Date: 2022/03/01 Vol. E105-A No. 3 pp. 518-529 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB), real-time operating system (RTOS), soft real-time scheduling,
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Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Yutaka MASUDA Jun NAGAYAMA TaiYu CHENG Tohru ISHIHARA Yoichi MOMIYAMA Masanori HASHIMOTO
Publication: Publication Date: 2022/03/01 Vol. E105-A No. 3 pp. 509-517 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: critical path isolation, bit-width scaling, voltage over-scaling, approximate computing,
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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Naoki HATTORI Jun SHIOMI Yutaka MASUDA Tohru ISHIHARA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1477-1487 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: neural network, optical circuit, multi-layer perceptron, wavelength division multiplexing,
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A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1546-1554 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1741-1750 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip,
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1751-1759 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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A Design Method of a Cell-Based Amplifier for Body Bias Generation Takuya KOYANAGI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 565-572 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: body bias generator, cell-based-design, analog-assisted digital, amplifier, low power,
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A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing Shu HOKIMOTO Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2776-2784 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB),
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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2764-2775 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB), standard-cell based memory (SCM),
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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2463-2472 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: latch, low voltage design, stability modeling,
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Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1455-1466 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: near-threshold computing, statistical static timing analysis (SSTA),
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An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2477-2487 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: energy optimization, compiler, profiler, real-time operating systems, embedded systems,
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DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems Kyungsoo LEE Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2660-2667 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: task scheduling, power loss reduction, DC-DC converter, energy harvesting, reconfigurable, PV cell, supercapacitor,
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Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation Shinichi NISHIZAWA Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 pp. 2499-2507 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: standard cell design, low power circuit design, near threshold operation, PN ratio optimization,
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Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications Lovic GAUTHIER Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2597-2608 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: stack, scratch-pad memory, energy consumption reduction, embedded systems,
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A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2533-2541 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: microprocessor, low-power design, embedded systems, real-time systems,
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Way-Scaling to Reduce Power of Cache with Delay Variation Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3576-3584 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: leakage, power reduction, cache, within-die variation, delay variation, way scaling,
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 410-417 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: single event upset, SRAM, DRAM, reliability, cache architecture, task scheduling,
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Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1983-1991 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: VLSI Design Technology Keyword: soft error, reliability, estimation, computer systems, instruction-set simulation,
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A System Level Optimization Technique for Application Specific Low Power Memories Tohru ISHIHARA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2755-2761 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: low power design, hardware/software codesign, memory, low voltage, embedded system,
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System LSI Design Methods for Low Power LSIs Hiroto YASUURA Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 143-152 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: low power design, system level, optimization, hardware/software codesign,
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A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/25 Vol. E83-C No. 2 pp. 186-194 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: cache, low power, low energy, way prediction, high performance,
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A Memory Power Optimization Technique for Application Specific Embedded Systems Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2366-2374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: low power design, hardware/software codesign, memory, embedded system,
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Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2621-2629 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Compiler Keyword: compiler optimization, instruction scheduling, low power, caches,
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Programmable Power Management Architecture for Power Reduction Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 pp. 1473-1480 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: low power design, power management, CMOS VLSI processor,
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Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 480-486 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: CMOS VLSI circuits, low power design, power estimation,
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