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IEICE Trans

Yuta UKON

Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism
Yuta UKON Shimpei SATO Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2021/07/01
Vol. E104-C  No. 7  pp. 309-318
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
digital circuit design, variable-latency circuit, signal monitoring, approximate completion-detection mechanism, 
 Summary | Full Text:PDF
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
Yuta UKON Koji YAMAZAKI Koyo NITTA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2020/01/01
Vol. E103-B  No. 1  pp. 11-19
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architecture, Applications and Operation Technologies for a Cyber-Physical System)
Category: Network System
Keyword: 
service function chaining, real-time image processing, packet-reordering circuit, CPU-FPGA architecture, 
 Summary | Full Text:PDF
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution
Shimpei SATO Eijiro SASSA Yuta UKON Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1760-1769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
circuit design, variable-latency circuit, speculative execution, general-synchronous circuit, timing-error detection, 
 Summary | Full Text:PDF