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| Yusuke KANNO
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Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Makoto SAEN Tadanobu TOBA Yusuke KANNO | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2017/04/01
Vol. E100-C
No. 4
pp. 382-390
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
FPGA, soft-error tolerance, memory controller, configuration RAM, | | | Summary | Full Text:PDF | |
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µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO Hiroyuki MIZUNO Nobuhiro OODAIRA Yoshihiko YASU Kazumasa YANAGISAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4
pp. 589-597
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
low-cost, System-on-Chip, SoC, System-in-Package, SiP, hierarchical I/O design, signal-level converter, signal wall function, low-power, interconnect circuit, | | | Summary | Full Text:PDF | |
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