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IEICE Trans

Yasuhiro TAKASHIMA

Complexity and Exact Solution of Set-Pair Routing Problem
Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3  pp. 590-595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
set-pair routing problem, NP-hard, integer linear programming, 
 Summary | Full Text:PDF
A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs
Tieyuan PAN Lian ZENG Yasuhiro TAKASHIMA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2412-2424
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
fast MER enumeration, FPGAs, low memory consumption, 
 Summary | Full Text:PDF
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device
Tieyuan PAN Li ZHU Lian ZENG Takahiro WATANABE Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1345-1354
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
online task placement, reconfigurable device, efficient data structure, MER enumeration, 
 Summary | Full Text:PDF
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies
Masato INAGI Yuichi NAKAMURA Yasuhiro TAKASHIMA Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2572-2583
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
inter-FPGA routing, multi-FPGA system, prototyping, time-multiplexed I/O, 
 Summary | Full Text:PDF
An Effective Overlap Removable Objective for Analytical Placement
Syota KUWABARA Yukihide KOHIRA Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1348-1356
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
analytical placement, minimization of overlap area, overlap evaluation, 
 Summary | Full Text:PDF
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3539-3547
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
FPGA prototyping, ILP, I/O pins constraint, verification, time-multiplexed I/O, 
 Summary | Full Text:PDF
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation
Yuko HASHIZUME Yasuhiro TAKASHIMA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9  pp. 2322-2327
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
post-silicon clock-timing tuning, deskew, programmable delay element (PDE), linear programming, totally unimodular, 
 Summary | Full Text:PDF
A Relocation Method for Circuit Modifications
Kunihiko YANAGIBASHI Yasuhiro TAKASHIMA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2743-2751
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
non full-reverse-order constraint, circuit modification, relocation, sequence-pair, simulated annealing, 
 Summary | Full Text:PDF
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5  pp. 924-931
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit partitioning, time-multiplexed I/O, FPGA, pin constraint, 
 Summary | Full Text:PDF
The Oct-Touched Tile: A New Architecture for Shape-Based Routing
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 448-455
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog layout, shape-based routing, routing architecture, tile, 
 Summary | Full Text:PDF
A Device-Level Placement with Schema Based Clusters in Analog IC Layouts
Takashi NOJIMA Xiaoke ZHU Yasuhiro TAKASHIMA Shigetoshi NAKATAKE Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3301-3308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Layout
Keyword: 
device-level placement, rectangle packing, Sequence-Pair, directional convex, cluster-constraint, 
 Summary | Full Text:PDF
Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
Ning FU Shigetoshi NAKATAKE Yasuhiro TAKASHIMA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3224-3232
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
abstract floorplan, consistent floorplan, pillar, 
 Summary | Full Text:PDF
A Fast Algorithm for Crosspoint Assignment under Crosstalk Constraints with Shielding Effects
Keiji KIDA Xiaoke ZHU Changwen ZHUANG Yasuhiro TAKASHIMA Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3258-3264
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosspoint assignment (CPA), crosstalk, shielding effects, {d,1}-pitch constraint, maximum-cost-difference-assignment (MCDA), 
 Summary | Full Text:PDF
Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk
Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9  pp. 1909-1915
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
minimum cross-talk, assignment, intersecting interval sets, 
 Summary | Full Text:PDF
Routability of FPGAs with Extremal Switch-Block Structures
Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 850-856
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGA, switch-block, routability, detailed-routing, 
 Summary | Full Text:PDF