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On Easily Reconstructable Logic Functions
Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2024/08/01
Vol. E107-D
No. 8
pp. 913-921
Type of Manuscript:
Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category:
Keyword:
complexity of logic function, random function, monotone function, threshold function, logic minimization, partially defined function, classification, data mining, machine learning, generalization ability, | | | Summary | Full Text:PDF | |
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Classification Functions for Handwritten Digit Recognition
Tsutomu SASAO Yuto HORIKAWA Yukihiro IGUCHI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/08/01
Vol. E104-D
No. 8
pp. 1076-1082
Type of Manuscript:
Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword:
linear decomposition, partially defined function, support minimization, classification, digit recognition, MNIST, index generation function, machine learning, neural network, ensemble method, | | | Summary | Full Text:PDF | |
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A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D
No. 2
pp. 364-373
Type of Manuscript:
Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword:
regular expression, NFA, DFA, MNFAU, FPGA, | | | Summary | Full Text:PDF | |
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A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12
pp. 3471-3481
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword:
LUT cascade, bdd_for_cf, functional decomposition, | | | Summary | Full Text:PDF | |
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Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D
No. 7
pp. 1492-1500
Type of Manuscript:
Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword:
three-level network, logic minimization, adder, programmable logic, | | | Summary | Full Text:PDF | |
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Compact Representations of Logic Functions Using Heterogeneous MDDs
Shinobu NAGAYAMA Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A
No. 12
pp. 3168-3175
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword:
heterogeneous MDD, ROBDD, FBDD, APL, memory size, | | | Summary | Full Text:PDF | |
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FOREWORD
Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D
No. 5
pp. 909-909
Type of Manuscript:
FOREWORD
Category:
Keyword:
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FOREWORD
Tsutomu SASAO | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D
No. 10
pp. 973-973
Type of Manuscript:
FOREWORD
Category:
Keyword:
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